30.6 PLLA Clock

The PLLA clock (PLLACK) is generated from MAINCK by the PLLA and a predivider. This combination allows a wide range of frequencies to be selected on either MCK, HCLK or the PCKx outputs.

The following figure shows the block diagram of the dividers and PLLA blocks.

Figure 30-4. Divider and PLLA Block Diagram

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