37.4 Signal Interface
The GMAC includes the following signal interfaces:
- MII, RMII to an external PHY
- MDIO interface for external PHY management
- Slave APB interface for accessing GMAC registers
- Master AHB interface for memory access
- GTSUCOMP signal for TSU timer count value comparison
| Signal Name | Function | MII | RMII |
|---|---|---|---|
| GTXCK(1) | Transmit Clock or Reference Clock | TXCK | REFCK |
| GTXEN | Transmit Enable | TXEN | TXEN |
| GTX[3..0] | Transmit Data | TXD[3:0] | TXD[1:0] |
| GTXER | Transmit Coding Error | TXER | Not Used |
| GRXCK | Receive Clock | RXCK | Not Used |
| GRXDV | Receive Data Valid | RXDV | CRSDV |
| GRX[3..0] | Receive Data | RXD[3:0] | RXD[1:0] |
| GRXER | Receive Error | RXER | RXER |
| GCRS | Carrier Sense and Data Valid | CRS | Not Used |
| GCOL | Collision Detect | COL | Not Used |
| GMDC | Management Data Clock | MDC | MDC |
| GMDIO | Management Data Input/Output | MDIO | MDIO |
Note:
- Input only. GTXCK must be provided with a 25 MHz / 50 MHz external crystal oscillator for MII / RMII interfaces, respectively.