Full and half duplex operation at all supported speeds of operation
Statistics Counter Registers for
RMON/MIB
MII/RMII interface to the physical
layer
Integrated physical coding
Direct memory access (DMA) interface to external memory
Support for priority queues in
DMA
8-KByte transmit RAM and 4-KByte
receive RAM (refer to Table 37-4 for queue-specific sizes
Programmable burst length and endianism for DMA
Interrupt generation to signal receive and transmit completion, errors or other events
Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames
Automatic discard of frames received with errors
Receive and transmit IP, TCP and UDP checksum offload. Both IPv4 and IPv6 packet types supported
Address checking logic for four specific 48-bit addresses, four type IDs, promiscuous mode, hash matching of unicast and multicast destination addresses and Wake-on-LAN
Management Data Input/Output (MDIO) interface for physical layer management
Support for jumbo frames up to 10240
Bytes
Full duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames
Half duplex flow control by forcing collisions on incoming frames
Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames
Support for 802.1Qbb priority-based flow control
Programmable Inter Packet Gap (IPG) Stretch
Recognition of IEEE 1588 PTP frames
IEEE 1588 time stamp unit (TSU)
Support for 802.1AS timing and synchronization
Supports 802.1Qav traffic shaping on
two highest priority queues
Support for 802.3az Energy Efficient
Ethernet
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
