39.8.6 READ_SINGLE_BLOCK/READ_MULTIPLE_BLOCK Operation using DMA Controller

  1. Wait until the current command execution has successfully completed.

    a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.

  2. Program the block length in the card. This value defines the value block_length.
  3. Program the block length in the HSMCI Configuration Register with block_length value.
  4. Set RDPROOF bit in HSMCI_MR to avoid overflow.
  5. Configure the fields of the HSMCI_MR as follows:

    a. Program FBYTE to one when the transfer is not multiple of 4, zero otherwise.

  6. Issue a READ_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK command.
  7. Program the DMA controller.

    a. Read the Channel Status Register to choose an available (disabled) channel.

    b. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_CISx register.

    c. Program the channel registers.

    d. The DMAC_CSAx register for Channel x must be set with the starting address of the HSMCI_FIFO address.

    e. The DMAC_CDAx register for Channel x must be word aligned.

    f. Configure the fields of DMAC_CCx for Channel x as follows:

    – DWIDTH is set to WORD when the length is a multiple of 4, otherwise it is set to BYTE.

    – CSIZE must be set according to the value of HSMCI_DMA.CHKSIZE.

    g. Configure the fields of the DMAC_CUBCx register of Channel x as follows:

    – UBLEN is programmed with block_length/4 when the transfer length is multiple of 4, block_length otherwise.

    h. Enable Channel x, writing one to DMAC_GE.EN[x]. The DMAC is ready and waiting for request.

  8. Wait for XFRDONE in the HSMCI_SR.