8.2 System I/O Lines
System I/O lines are pins used by oscillators, Test mode, reset, JTAG and other features. The following table lists the SAM E70/S70/V70/V71 system I/O lines shared with PIO lines.
These pins are software-configurable as general-purpose I/Os or system pins. At startup, the default function of these pins is always used.
| CCFG_SYSIO Bit Number |
Default Function After Reset | Other Function | Constraints for Normal Start | Configuration |
|---|---|---|---|---|
| 12 | ERASE | PB12 | Low Level at startup (see Note 1) | In Matrix User Interface
Registers (Refer to the CCFG_SYSIO19.4.7 System I/O and CAN1 Configuration Register register) |
| 7 | TCK/SWCLK | PB7 | – | |
| 6 | TMS/SWDIO | PB6 | – | |
| 5 | TDO/TRACESWO | PB5 | – | |
| 4 | TDI | PB4 | – | |
| – | PA7 | XIN32 | – | (see Note 2 and 4) |
| – | PA8 | XOUT32 | – | |
| – | PB9 | XIN | – | (see Note 3 and 4) |
| – | PB8 | XOUT | – |
Note:
- If the PB12 pin is used as PIO input in user applications, a low level must be ensured at start up to prevent Flash erase before the user application sets the PB12 pin into PIO mode.
- Refer to 23.4.2 Slow Clock Generator.
- Refer to 30.5.3 Main Crystal Oscillator.
- If not used then the corresponding PIO pin must be setup as an output and attached to a dedicated trace on the board to reduce current consumption.