47.6.3.4 Memory Interface Block

The Memory Interface (MIF) block implements a bridge between the I/O and the CTB or DBB interfaces.

CTR Access

The MIF block allows the HC to directly access the external Channel Table RAM (CTR) when MLB_MADR.TB is cleared. Any write to the MLB_MADR register triggers a single read or write cycle. Reading from the MLB_MADR register does not initiate read/write access.

Figure 47-18. MIF CTR Read and Write Flow Diagrams

Direct CTR Writes

For a direct write of the CTR, the HC first loads the 128-bit data entry into the MLB_MDAT0–3 registers. Bitwise write enable control is available via the MLB_MDWE0–3 registers.

After the MDATn and MDWEn registers are set up, a write cycle is initiated by writing the address and control information to MLB_MADR as follows:

  • MLB_MADR.WNR = 1
  • MLB_MADR.TB = 0
  • MLB_MADR.ADDR[7:0] = 8-bit Target Address

The MIF block sets MLB_MCTL.XCMP = 1 to inform the HC when the write is complete.

Direct CTR Reads

For a direct read of the CTR, the HC initiates a read cycle by writing the address and control information to MLB_MADR as follows:

  • MLB_MADR.WNR = 0
  • MLB_MADR.TB = 0
  • MLB_MADR.ADDR[7:0] = 8-bit Target Address

The MIF block sets MLB_MCTL.XCMP = 1 to inform the HC when the read is complete. The HC can then read the 128-bit data entry from the MLB_MDAT0–3 registers.

CTR Addressing

The CTR is addressed as a 128-bit wide value. However, the MIF block can only access 32 bits of the addressed CTR data in a single access. Therefore, four 32-bit accesses through the MIF block are required to access a single 128-bit value (e.g. CDT entry).

To access a 16-bit CAT entry in the CTR, only a single access through the MIF is required. For example, to load a CAT61 entry for an isochronous Tx channel with mute and flow control enabled:

  • Write MLB_MDAT2 = 7B070000h (assumes Connection Label = 7)
  • MLB_MDWE2 = FFFF0000h (bitwise write enable for 16 msbs; 
assumes MLB_MDWE0/1/3 =00000000h)
  • MLB_MADR = 80000087h (write CTR address 87h)

DBR Access

The MIF block allows the HC to access the external Data Buffer RAM (DBR) directly when MLB_MADR.TB is set. Any write to the MLB_MADR triggers a single read or write cycle. Reading from the MLB_MADR register does not initiate read/write access.

Figure 47-19. MIF DBR Read and Write Flow Diagrams

Direct DBR Writes

For a direct write of the DBR, the HC first loads the 8-bit data entry into the MLB_MDAT0 register at bits[7:0]. MLB_MDAT1–3 and MLB_MDWE0–3 are not used for DBR access.

After the MLB_MDAT0 register is set up, a write cycle is initiated by writing the address and control information to MLB_MADR as follows:

  • MLB_MADR.WNR = 1
  • MLB_MADR.TB = 1
  • MLB_MADR.ADDR[13:0] = 14-bit Target Address

The MIF block sets MLB_MCTL.XCMP = 1 to inform the HC when the write is complete.

Direct DBR Reads

For a direct read of the DBR, the HC initiates a read cycle by writing the address and control information to MLB_MADR as follows:

  • MLB_MADR.WNR = 0
  • MLB_MADR.TB = 1
  • MLB_MADR.ADDR[13:0] = 14-bit target address

The MIF block sets MLB_MCTL.XCMP = 1 to inform the HC when the read is complete. The HC can then read the 8-bit data entry from the MLB_MDAT0 register at bits[7:0].