34.11.1 Chip Select Wait States

The SMC always inserts an idle cycle between two transfers on separate Chip Selects. This idle cycle ensures that there is no bus contention between the deactivation of one device and the activation of the next one.

During Chip Select Wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1.

The following figure illustrates a Chip Select Wait state between access on Chip Select 0 and Chip Select 2.

Figure 34-17. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2

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