31.7 USB Full-speed Clock Controller

The user can select the PLLA or the UPLL output as the USB FS clock (USB_48M) by writing a ‘1’ to the USBS bit in the USB Clock Register (PMC_USB). The user then must program the corresponding PLL to generate an appropriate frequency depending on the USBDIV bit in PMC_USB.

When PMC_SR.LOCKA and PMC_SR.LOCKU are set to ‘1’, the PLLA and UPLL are stable. Then, USB_48M can be enabled by setting the USBCLK bit in the System Clock Enable register (PMC_SCER). To save power on this peripheral when not used, the user can set the USBCLK bit in the System Clock Disable register (PMC_SCDR). The USBCLK bit in the System Clock Status register (PMC_SCSR) gives the status of this clock. The USB port requires both the USB clock signal and the peripheral clock. The USB peripheral clock is controlled by means of the Host Clock Controller.