31.8 Core and Bus Independent Clocks for Peripherals

The following table lists the peripherals that require a PCKx clock to operate while the core, bus and peripheral clock frequencies are modified, thus providing communications at a bit rate which is independent for the core/bus/peripheral clock. This mode of operation is possible by using the internally generated independent clock sources.

Internal clocks can be independently selected between SLCK, MAINCK, any available PLL clock, and MCK by configuring PMC_PCKx.CSS. The independent clock sources can be also divided by configuring PMC_PCKx.PRES.

Each internal clock signal (PCKx) can be enabled and disabled by writing a ‘1’ to the corresponding PMC_SCER.PCKx and PMC_SCDR.PCKx, respectively. The status of the internal clocks are given in PMC_SCSR.PCKx.

The status flag PMC_SR.PCKRDYx indicates that the programmable internal clock has been programmed in the Programmable clock registers.

The independent clock source must also be selected in each peripheral in the Clock Assignments table to operate communications, timings, etc without influencing the frequency of the core/bus/peripherals (except frequency limitations listed in each peripheral).

Note: USB, GMAC and MLB do not require PCKx to operate independently of core and bus peripherals.