12.9.6 PIR1

Peripheral Interrupt Request Register 1

Note:

RC1IF is read-only. User software must read RC1REG to clear RC1IF.
TX1IF is read-only. User software must load TX1REG to clear TX1IF. TX1IF does not indicate a completed transmission (use TMRT for this purpose instead).
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable (GIE) bit. User software needs to ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.

Name:	PIR1
Offset:	0x70D


Bit	7	6	5	4	3	2	1	0
	CCP1IF	TMR2IF	TMR1IF	RC1IF	TX1IF	BCL1IF	SSP1IF	ADIF
Access	R/W/HS	R/W/HS	R/W/HS	R	R	R/W/HS	R/W/HS	R/W/HS
Reset	0	0	0	0	0	0	0	0

Bit 7 – CCP1IF CCP1 Interrupt Flag


Value	CCP Mode
Value	Capture	Compare	PWM
`1`	Capture occurred (must be cleared in software)	Compare match occurred (must be cleared in software)	Output trailing edge occurred (must be cleared in software)
`0`	Capture did not occur	Compare match did not occur	Output trailing edge did not occur

Bit 6 – TMR2IF TMR2 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared in software)
0	Interrupt event has not occurred

Bit 5 – TMR1IF TMR1 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared in software)
0	Interrupt event has not occurred

Bit 4 – RC1IF EUSART1 Receive Interrupt Flag⁽¹⁾

Value	Description
1	The EUSART1 receive buffer (RC1REG) is not empty (contains at least one byte)
0	The EUSART1 receive buffer is empty

Bit 3 – TX1IF EUSART1 Transmit Interrupt Flag⁽²⁾

Value	Description
1	The EUSART1 transmit buffer (TX1REG) is empty
0	The EUSART1 transmit buffer is not empty

Bit 2 – BCL1IF MSSP1 Bus Collision Interrupt Flag

Value	Description
1	A bus collision was detected (must be cleared in software)
0	No bus collision was detected

Bit 1 – SSP1IF MSSP1 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared in software)
0	Interrupt event has not occurred

Bit 0 – ADIF ADC Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared in software)
0	Interrupt event has not occurred

RC1IF is read-only. User software must read RC1REG to clear RC1IF.TX1IF is read-only. User software must load TX1REG to clear TX1IF. TX1IF does not indicate a completed transmission (use TMRT for this purpose instead).Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable (GIE) bit. User software needs to ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.