12.9.4 PIE2

Peripheral Interrupt Enable Register 2
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by PIE1 and PIE2 registers.
Name: PIE2
Offset: 0x718

Bit 76543210 
 CCP2IENVMIETMR1GIE      
Access R/WR/WR/W 
Reset 000 

Bit 7 – CCP2IE CCP2 Interrupt Enable

ValueDescription
1 CCP2 interrupts are enabled
0 CCP2 interrupts are disabled

Bit 6 – NVMIE NVM Interrupt Enable

ValueDescription
1 NVM interrupts are enabled
0 NVM interrupts are disabled

Bit 5 – TMR1GIE TMR1 Gate Interrupt Enable

ValueDescription
1 TMR1 Gate interrupts are enabled
0 TMR1 Gate interrupts are disabled
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by PIE1 and PIE2 registers.