12.9.5 PIR0

Peripheral Interrupt Request Register 0
Note:
  1. The external interrupt INT pin is selected by INTPPS.
  2. The IOCIF bit is the logical OR of all the IOCAF-IOCCF flags. Therefore, to clear the IOCIF flag, application firmware must clear all of the lower level IOCAF-IOCCF register bits.
  3. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable (GIE) bit. User software needs to ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name: PIR0
Offset: 0x70C

Bit 76543210 
   TMR0IFIOCIF   INTF 
Access R/W/HSRR/W/HS 
Reset 000 

Bit 5 – TMR0IF Timer0 Interrupt Flag

ValueDescription
1 TMR0 register has overflowed (must be cleared by software)
0 TMR0 register has not overflowed

Bit 4 – IOCIF  Interrupt-on-Change Flag(2)

ValueDescription
1 One or more of the IOCAF-IOCCF register bits are currently set, indicating an enabled edge was detected by the IOC module.
0 None of the IOCAF-IOCCF register bits are currently set

Bit 0 – INTF  External Interrupt Flag(1)

ValueDescription
1 External interrupt has occurred
0 External interrupt has not occurred
The external interrupt INT pin is selected by INTPPS. The IOCIF bit is the logical OR of all the IOCAF-IOCCF flags. Therefore, to clear the IOCIF flag, application firmware must clear all of the lower level IOCAF-IOCCF register bits. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable (GIE) bit. User software needs to ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.