2.2.2 Inputs and Outputs Signals

The following table lists the input and output ports of BLDC estimator.

Table 2-4. Inputs and Outputs of BLDC Estimator
Signal Name	Direction	Description
reset_i	Input	Active low synchronous reset signal
sys_clk_i	Input	System clock
start_i	Input	Start signal to start module computation - must be high for one system clock cycle
clear_buffer_i	Input	When set to 1, internal speed filter buffer is cleared. When set to 0, buffer is normally operated.
angle_pi_en_i	Input	Enable signal for PLL PI controller
v_alpha_i	Input	Alpha axis voltage input for angle estimation
v_beta_i	Input	Beta axis voltage input for angle estimation
i_alpha_i	Input	Alpha axis current input for angle estimation
i_beta_i	Input	Beta axis current input for angle estimation
Ls_by_Ts_pu_i	Input	Motor Inductance L (in per unit) / sampling time
Rs_pu_i	Input	Motor Resistance R (in per unit)
ealpha_filter_factor_i	Input	Represents the Ealpha filter time constant – input as an exponent of 2 2^(ealpha_filter_factor_i) * sampling time
ebeta_filter_factor_i	Input	Represents the Ebeta filter time constant – input as an exponent of 2 2^(ebeta_filter_factor_i) * sampling time
pll_theta_factor_i	Input	Theta factor value
angle_pi_kp_i	Input	Proportional constant for angle PI
angle_pi_ki_i	Input	Integral constant for angle PI
omega_filter_factor_i	Input	Represents the speed filter time constant – input as an exponent of 2 2^(omega_filter_factor_i) * sampling time
done_o	Output	Indicates completion of speed computation. High for one clock cycle.
theta_o	Output	Estimated angle (theta) output
ealpha_o	Output	Back-emf on alpha axis
ebeta_o	Output	Back-emf on beta axis
ealpha_filtered_o	Output	Filtered back-emf on alpha axis
ebeta_filtered_o	Output	Filtered back-emf on beta axis
pll_pi_out_o	Output	Speed output from PLL
speed_filtered_o	Output	Filtered speed output