17.2.1 Inputs and Outputs Signals
(Ask a Question)The following table lists the input and output ports of SVM.
| Signal Name | Direction | Description |
|---|---|---|
| sys_clk_i | Input | System clock |
| reset_i | Input | Active Low asynchronous reset signal to design |
| start_i | Input | A single bit start signal that must go high for one clock cycle to start SVM computations |
| va_i | Input | Input phase voltage (va) |
| vb_i | Input | Input phase voltage (vb) |
| vc_i | Input | Input phase voltage (vc) |
| va3h_o | Output | Output voltage signal corresponding to input phase voltage va_i, with the third harmonic component |
| vb3h_o | Output | Output voltage signal corresponding to input phase voltage vb_i, with the third harmonic component |
| vc3h_o | Output | Output voltage signal corresponding to input phase voltage vc_i, with the third harmonic component |
| done_o | Output | A single bit signal which goes High for one clock cycle to indicate that all the computations are done and output corresponding to given inputs is obtained |