14.2.2 Input and Output Signals
(Ask a Question)The following table lists the input and output ports of Sinc3 Filter.
| Signal Name | Direction | Description |
|---|---|---|
| reset_i | Input | Active low asynchronous reset signal to design |
| clk_adc_i | Input | Modulator clock coming from ADC |
| data_adc_i | Input | Data bitstream from the modulator in ADC |
| reg_rst_i | Input | When 1, resets all the registers. When 0, filter is normally operated. |
| clk_dec_o | Output | Decimated clock output. This is the same clock used for differentiator. The output of the filter updates at the rising edge of this output. This signal is not generated when res_rst_i is high. |
| data_o | Output | Filtered data output |