8.2.2 Input and Output Signals

The following table lists the input and output ports of Open-Loop Manager.

Table 8-3. Inputs and Outputs of Open-Loop Manager
Signal Name	Direction	Description
reset_i	Input	Asynchronous active low reset signal
sys_clk_i	Input	System Clock
start_i	Input	Start signal to start module computation - should be high for one system clock cycle
clear_buffer_i	Input	When high, internal buffers are set to zero
direction_config_i	Input	Motor Direction input
cl_status_i	Input	Closed-loop status
theta_factor_i	Input	Theta factor (constant) input
speed_ref_i	Input	Motor speed reference input
dv_i	Input	Delta Voltage to add to Vq (through init value of IQ PI controller)
theta_cl_i	Input	Closed-loop angle value
iq_ref_in_i	Input	Iq Current Reference value
done_o	Output	Indicates completion of module computations – high for one clock cycle
theta_o	Output	Angle output: When cl_status_i is set to 0, output is open-loop angle (computed internally) When cl_status_i is set to 1, output is closed-loop angle (from theta_cl_i input)
init_speedpi_o	Output	init value for speed PI controller
init_iqpi_o	Output	init value for Iq PI controller