10.2.2 Inputs and Outputs Signals

The following table lists the input and output ports of PWM Scaling.

Table 10-3. Inputs and Outputs of PWM Scaling
Signal Name	Direction	Description
reset_i	Input	Active low asynchronous reset signal
sys_clk_i	Input	System clock
start_i	Input	A single bit start signal that must go high for one clock cycle to start PWM scaling computations.
va_i	Input	Phase A voltage input
vb_i	Input	Phase B voltage input
vc_i	Input	Phase C voltage input
pwm_period_i	Input	PWM period value in number of system clock cycles
pwm_gain_i	Input	PWM gain input
va_o	Output	Scaled phase A voltage output
vb_o	Output	Scaled phase B voltage output
vc_o	Output	Scaled phase C voltage output
done_o	Output	Indicates completion of scaling operations is high for one clock cycle