6.3 Timing Diagrams

This section discusses Median Filter timing diagrams.

The following figure shows the timing diagram of Median Filter.

After the reset signal is de-asserted, the window will have all zeros. The first input sample will enter the window at the first rising edge of dec_clk_i, the second sample will enter the window at the second rising edge of dec_clk_i and so on.

For the timing diagram shown in the above-mentioned figure, after the reset signal is de-asserted, the window will be {0,0,0,0,0,0,0,0,0}

At first rising edge of dec_clk_i , data_i is 0, the window will be{0,0,0,0,0,0,0,0,0}

At second rising edge of dec_clk_i,data_i is 1,the window will be{0,0,0,0,0,0,0,0,1}

At third rising edge of dec_clk_i,data_i is 2,the window will be{0,0,0,0,0,0,0,0,1,2} and so on.