6.2.2 Inputs and Outputs Signals

The following table lists the input and output ports of Median Filter.

Table 6-4. Inputs and Outputs of Median Filter
Signal Name	Direction	Width	Description
reset_i	Input	1bit	Active low asynchronous reset signal to design
sys_clk_i	Input	1bit	System clock
dec_clk_i	Input	1bit	Decimated clock input - data is sampled at the rising edge of this signal
en_i	Input	1bit	Enables signal
data_i	Input	g_DATA_WIDTH bits	Data input
data_o	Output	g_DATA_WIDTH bits	Median data output