12.5.9 FSCMCON

Fail-Safe Clock Monitor Control and Status Register
Note:
  1. This bit is used to demonstrate that FSCM can detect clock failure; the bit must be cleared for normal operation.
  2. This bit will not be cleared by hardware upon clock recovery; the bit must be cleared by the user.
Name: FSCMCON
Address: 0x082

Bit 76543210 
   FSCMSFIFSCMSEVFSCMPFIFSCMPEVFSCMFFIFSCMFEV 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 5 – FSCMSFI  SOSC Fail-Safe Clock Monitor Fault Injection(1)

ValueDescription
1 SOSC FSCM clock input is blocked; FSCM will time-out
0 SOSC FSCM clock input is enabled; FSCM functions as indicated

Bit 4 – FSCMSEV  SOSC Fail-Safe Clock Monitor Status(2)

ValueDescription
1 SOSC clock showed a failure
0 FSCM is detecting SOSC input clocks, or the bit was cleared by the user

Bit 3 – FSCMPFI  Primary Oscillator Fail-Safe Clock Monitor Fault Injection(1)

ValueDescription
1 Primary Oscillator FSCM clock input is blocked; FSCM will time-out
0 Primary Oscillator FSCM clock input is enabled; FSCM functions as indicated

Bit 2 – FSCMPEV  Primary Oscillator Fail-Safe Clock Monitor Status(2)

ValueDescription
1 Primary Oscillator clock showed a failure
0 FSCM is detecting primary oscillator input clocks, or the bit was cleared by the user

Bit 1 – FSCMFFI  FOSC Fail-Safe Clock Monitor Fault Injection(1)

ValueDescription
1 FOSC FSCM clock input is blocked; FSCM will time-out
0 FOSC FSCM clock input is enabled; FSCM functions as indicated

Bit 0 – FSCMFEV  FOSC Fail-Safe Clock Monitor Status(2)

ValueDescription
1 FOSC clock showed a failure
0 FSCM is detecting FOSC input clocks, or the bit was cleared by the user
This bit is used to demonstrate that FSCM can detect clock failure; the bit must be cleared for normal operation. This bit will not be cleared by hardware upon clock recovery; the bit must be cleared by the user.