45.3.1 Supply Voltage

Table 45-1.
Standard Operating Conditions (unless otherwise stated)
Param. No.	Sym.	Characteristic	Min.	Typ.†	Max.	Units	Conditions
Supply Voltage
D002	V_DD		1.8	—	5.5	V
D002A	V_DDIOx		1.62	—	5.5	V
RAM Data Retention⁽¹⁾
D003	V_DR		1.7	—	—	V	Device in Sleep mode; on V_DD domain
Power-on Reset Release Voltage⁽²⁾
D004	V_POR		—	1.6	1.8	V	BOR and LPBOR disabled⁽³⁾; on V_DD domain
D004A	V_PORVDDIOx		—	1.6	1.62	V	V_{DDIOx domain}
Power-on Reset Rearm Voltage⁽²⁾
D005	V_PORR		—	1	—	V	BOR and LPBOR disabled⁽³⁾; on V_DD domain
D005A	V_PORRVDDIOx		—	1	—	V	V_DDIOx domain
V_DD Rise Rate to ensure internal Power-on Reset signal⁽²⁾
D006*	S_VDD		0.05	—	—	V/ms	BOR and LPBOR disabled⁽³⁾; on V_DD domain
D006A*	S_VDD		—	—	1.2	V/μs	1.8V ≤ V_DD ≤ 5.5V
D007*	S_VDDIOx		0.05	—	—	V/ms	V_DDIOx domain
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: This is the limit to which V_DD can be lowered in Sleep mode without losing RAM data. See the following figure, POR and POR REARM with Slow Rising V_DD. See Reset, WDT, Oscillator Start-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications for BOR and LPBOR trip point information.

Figure 45-2. POR and POR Rearm with Slow Rising V_DD