45.4.5 Reset, WDT, Oscillator Start-Up Timer, Power-Up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications

Figure 45-7. Reset, Watchdog Timer, Oscillator Start-Up Timer and Power-Up Timer Timing
Note:
  1. Asserted low.
Figure 45-8. Brown-out Reset Timing and Characteristics
Note:
  1. Only if the PWRTE Configuration bit is programmed to ‘1’; 2 ms delay if PWRTE = 0.
Table 45-11. 
Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
RST01*TMCLRMCLR Pulse Width Low to ensure Reset—0.4—μs
RST02*TIOZI/O high-impedance from Reset detection——2μs
RST03*TWDTWatchdog Timer Time-out Period—2—msWDTCPS = 00001
RST04*TPWRTPower-up Timer Period—65—msPWRTS = 10
RST05*TOSTOscillator Start-up Timer Period(1,2)—1024—TOSC
RST06VBORBrown-out Reset Voltage2.72.853.0V

BORV = 00

2.552.72.85V

BORV = 01

2.32.452.6V

BORV = 10

1.81.92.1V

BORV = 11

RST07VBORHYSBrown-out Reset Hysteresis—60—mVBORV = 00
RST08*TBORDCBrown-out Reset Response Time—3—μs
RST09VLPBORLow-Power Brown-out Reset Voltage1.81.92.4V
RST09A*VLPBORHYSLow-Power Brown-out Reset Hysteresis—30—mV

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
  2. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.