32.17.2 Host Start-of-Frame Control

During a very short period just before transmitting a Start-of-Frame, this register is locked. Thus, after writing, it is recommended to check the register value, and write this register again if necessary. This register is cleared upon a USB reset.
Name: HSOFC
Offset: 0x0A
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
 FLENCE   FLENC[3:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 7 – FLENCE Frame Length Control Enable

When this bit is '1', the time between Start-of-Frames can be tuned by up to +/-0.06% using FLENC[3:0].
Note: In Low Speed mode, FLENCE must be '0'.
FLENCEFrame TimingInternal Frame Length Down-Counter Load Value
0Internal Frame Length (Full Speed)11999 (1ms frame rate at 12MHz)
0Internal Frame Length in Low and Full speed59999 (1ms frame rate at 60MHz)
Internal Frame Length in High speed7499 (0.125ms micro-frame rate at 60MHz)
1Beginning of FrameFLENC[3:0]
Internal Frame Length with Frame correction11999 + FLENC[3:0] at all speeds.
ValueDescription
0Start-of-Frame is generated every 1ms.
1Start-of-Frame generation depends on the signed value of FLENC[3:0].

USB Start-of-Frame period equals 1ms + (FLENC[3:0]/12000)ms

Bits 3:0 – FLENC[3:0] Frame Length Control

These bits define the signed value of the 4-bit FLENC that is added to the Internal Frame Length when FLENCE is '1'. The internal Frame length is the top value of the frame counter when FLENCE is zero.