34.8.11 Comparator Control n
| Name: | COMPCTRL |
| Offset: | 0x10 + n*0x04 [n=0..1] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FLEN[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| HYST | OUT[1:0] | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SWAP | MUXPOS[1:0] | MUXNEG[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INTSEL[1:0] | SPEED[1:0] | SINGLE | ENABLE | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 26:24 – FLEN[2:0] Filter Length
These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | No filtering |
| 0x1 | MAJ3 | 3-bit majority function (2 of 3) |
| 0x2 | MAJ5 | 5-bit majority function (3 of 5) |
| 0x3-0x7 | N/A | Reserved |
Bit 19 – HYST Hysteresis Enable
This bit indicates the Hysteresis mode of comparator n. Hysteresis is available only for Continuous mode (COMPCTRLn. SINGLE=0). COMPCTRLn.HYST can be written only while COMPCTRLn.ENABLE is zero.
This bit is not synchronized.
| Value | Name |
|---|---|
| 0 | Hysteresis is disabled. |
| 1 | Hysteresis is enabled. |
Bits 17:16 – OUT[1:0] Output
These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | The output of COMPn is not routed to the COMPn I/O port |
| 0x1 | ASYNC | The asynchronous output of COMPn is routed to the COMPn I/O port |
| 0x2 | SYNC | The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port |
| 0x3 | N/A | Reserved |
Bit 15 – SWAP Swap Inputs and Invert
This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
| Value | Description |
|---|---|
| 0 | The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative input. |
| 1 | The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative input. |
Bits 13:12 – MUXPOS[1:0] Positive Input Mux Selection
These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | PIN0 | I/O pin 0 |
| 0x1 | PIN1 | I/O pin 1 |
| 0x2 | PIN2 | I/O pin 2 |
| 0x3 | PIN3 | I/O pin 3 |
Bits 10:8 – MUXNEG[2:0] Negative Input Mux Selection
These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can only be written while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | PIN0 | I/O pin 0 |
| 0x1 | PIN1 | I/O pin 1 |
| 0x2 | PIN2 | I/O pin 2 |
| 0x3 | PIN3 | I/O pin 3 |
| 0x4 | GND | Ground |
| 0x5 | VSCALE | VDD scaler |
| 0x6 | BANDGAP | Internal bandgap voltage |
| 0x7 | DAC | DAC output |
Bits 6:5 – INTSEL[1:0] Interrupt Selection
These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | TOGGLE | Interrupt on comparator output toggle |
| 0x1 | RISING | Interrupt on comparator output rising |
| 0x2 | FALLING | Interrupt on comparator output falling |
| 0x3 | EOC | Interrupt on end of comparison (single-shot mode only) |
Bits 3:2 – SPEED[1:0] Speed Selection
This bit indicates the Speed/Propagation Delay mode of comparator n. COMPCTRLn.SPEED can be written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | LOW | Low speed |
| 0x1 | HIGH | High speed |
| 0x2-0x3 | N/A | Reserved |
Bit 1 – SINGLE Single-Shot Mode
This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
| Value | Description |
|---|---|
| 0 | Comparator n operates in Continuous Measurement mode. |
| 1 | Comparator n operates in Single-shot mode. |
Bit 0 – ENABLE Enable
Writing a zero to this bit disables comparator n. Writing a one to this bit enables comparator n. After writing to this bit, the value read back will not change until the action initiated by the writing is complete.
Due to synchronization, there is a latency of at least two GCLK_AC_DIG clock cycles from updating the register until the comparator is enabled/disabled. The bit will continue to read the previous state while the change is in progress. Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized.