34.8.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized

Bit 76543210 
 LPMUX    RUNSTDBYENABLESWRST 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 7 – LPMUX Low-Power Mux

This bit is not synchronized

ValueDescription
0 The analog input muxes have low resistance, but consume more power at lower voltages (e.g., are driven by the voltage doubler).
1 The analog input muxes have high resistance, but consume less power at lower voltages (e.g., the voltage doubler is disabled).

Bit 2 – RUNSTDBY Run in Standby

This bit controls the behavior of the comparators during standby sleep mode.

This bit is not synchronized

ValueDescription
0 The comparator pair is disabled during sleep.
1 The comparator pair continues to operate during sleep.

Bit 1 – ENABLE Enable

Due to synchronization, there is a delay from the time when the register is updated until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately after being written. STATUS.SYNCBUSY is set. STATUS.SYNCBUSY is cleared when the peripheral is enabled/disabled

ValueDescription
0 The AC is disabled.
1 The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the Comparator Control register (COMPCTRLn.ENABLE).

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the AC to their initial state, and the AC will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete.

ValueDescription
0 There is no reset operation ongoing.
1 The reset operation is ongoing.