47.7.21 Period Buffer Value
Note: This register must be written with 32 bit accesses only
(no 8 or 16 bit writes).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PERBUF |
| Offset: | 0x6C |
| Reset: | 0xFFFFFFFF |
| Property: | Write-Synchronized, Read-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PERBUF[25:18] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PERBUF[17:10] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PERBUF[9:2] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PERBUF[1:0] | DITHERBUF[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 31:6 – PERBUF[25:0] Period Buffer Value
These bits hold the value of the Period Buffer register. The value is copied to PER register on UPDATE condition.
Note: This bit field occupies the MSB
of the register, [31:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION(CTRLA <6:5>)):
| CTRLA.RESOLUTION | Bits [31:m] |
|---|---|
| 0x0 - NONE | 31:0 |
| 0x1 - DITH4 | 31:4 |
| 0x2 - DITH5 | 31:5 |
| 0x3 - DITH6 | 31:6 (depicted) |
Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number
Note: This bit field consists of the n
LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION(CTRLA <6:5>)):
| CTRLA.RESOLUTION(CTRLA <6:5>) | Bits [n:0] |
|---|---|
| 0x0 - NONE | - |
| 0x1 - DITH4 | 3:0 |
| 0x2 - DITH5 | 4:0 |
| 0x3 - DITH6 | 5:0 (depicted) |