16.10 Security Enforcement

Security enforcement aims at protecting intellectual property, it consists of the following:

  • Restricting access to access ports depending on the debugger access level and APDIS fuse configuration.
  • Restricting access to internal memories from external tools depending on the debugger access level.

The security at the Debug Access Port x level is enforced by setting the Debugger Access Level x bits in the DAL register (DAL.CPUx) to a value lower than 0x2. The DAL.CPUx setting can be elevated using Boot ROM commands depending on the Boot ROM user configuration, refer to chip-erase and Challenge/Response features in the “Boot ROM” chapter. When DAL.CPU0 is equal to 0 or 3, read/write accesses using the MEM-AP0 are limited to the DSU external address range and DSU commands are restricted. When issuing a (Host) Boot ROM Chip-Erase, sensitive Host information is erased from volatile memory and Flash. For more information about the (Host) Boot ROM features, such as the chip-erase, refer to the Boot ROM chapter. When x>0 and DAL.CPUx is equal to 0 all accesses to the MEM-APx are disabled.

The DSU implements an internal bus matrix which routes all AHB-AP0 accesses directed to the DSU address space directly to the DSU APB interface. Other access are routed to the CPU0 debug port, refer to the DSU Block Diagram).

The DSU also implements a Debug Authentication module that controls each AP and CPU debug feature depending on the CPU’s DAL level. When STATUSB.APDIS = 1 all MEM-AP instances are disabled (DP access to the MEM-AP registers are still permitted but a DAP fault is returned when a AHB transfer is attempted). When STATUSB.APDIS = 0 and DAL.CPUx = 0, the CPUx AHB debug port doesn’t accept debug transactions, any MEM-APx transaction returns a bus error which translates to an ARM DP sticky error bit (refer to the Arm Debug Interface v5 Architecture Specification on www.arm.com).

The DSU APB interface address space is divided as follows:

  • The first 0x100 bytes form the internal address range.
  • The next 0x1F00 bytes form the external address range.

Transactions initiated by a debug adapter are denoted as external transactions. All transactions directed to the CPU0 bus system go through the DSU Bus Matrix (BMX) which:

  • Allows access to the full address space when DAL>0.
  • Restricts accesses to the DSU external space when DAL= 0.
Figure 16-5. APB Memory Mapping
Table 16-1. MEM-AP0 Access Rights Depending on DAL.CPU0
Regions DAL.CPU0

(STATUSB.APDIS=0)
0 (3) 1 2 3
PPB or IOBUS N Y(1) Y N
DSU internal address space N N(2) Y N
DSU external address space Y Y Y Y
Other N Y Y N
Note:
  1. Refer to Arm v8m debug documentation for detailed information on PPB and IOBUS access restrictions.
  2. When DAL.CPU0 = 1 DAP transfers are always non-secure. The internal address space is accessible only by secure hosts. DAP transactions will propagate to the DSU APB interface but will be ignored and STATUSA.PERR will be set.
  3. MEM-AP0 is disabled until cold-plugging occurs.

Some features not activated by APB transactions are not available when the device is protected:

Table 16-2. Feature Availability Under Protection
Features DAL.CPU0
0 1 2 3
CPU Reset Extension Y Y Y Y
Clear CPU Reset Extension Y Y Y Y
Debugger Cold-Plugging Y Y Y Y
Debugger Hot-Plugging N Y Y N