15.4 Peripheral Dependencies
| Peripheral Name | Base Address | NVIC IRQ Index: Source | MCLK AHBx/APBx Clock Enable Mask Bit |
PAC Peripheral Identifier
(PAC.WRCTRL.PERIDx) |
EVSYS Generator
(EVSYS.CHANNELn.EVGENx) |
Power Domain |
|---|---|---|---|---|---|---|
| PAC | 0x4401_C000 | 30 : ERR | AHB: MCLK.CLKMSK0[6] APB: MCLK.CLKMSK1[14] | 14 | 37 : ACCERR | VDDREG |
Debug Operation
When the CPU is halted in Debug mode, write protection of all peripherals is disabled and the PAC continues normal operation.
Register Access Protection
All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:
- The Write Control (WRCTRL) register
- The Peripheral Interrupt Flag Status and Clear n (INTFLAG A/B/C...) registers
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description.
PAC write protection does not apply to accesses through an external debugger.