15.6 Register Summary

For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	WRCTRL	7:0	PERID[7:0]
		15:8	PERID[15:8]
		23:16	KEY[7:0]
		31:24
0x04	EVCTRL	7:0								ERREO
0x05 ... 0x07	Reserved
0x08	INTENCLR	7:0								ERR
0x09	INTENSET	7:0								ERR
0x0A ... 0x13	Reserved
0x14	INTFLAGA	7:0	OSC32KCTRL	OSCCTRL	RSTC	SUPC	PM	FCW	FCR	DSU
		15:8	TRAM	PAC	EIC	RTC	WDT	FREQM	MCLK	GCLK
		23:16
		31:24
0x18	INTFLAGB	7:0	SERCOM1	SERCOM0	EVSYS	IDAU	PRM	DMA1	DMA0	PORT
		15:8			TCC3	TCC2	TCC1	TCC0	SERCOM3	SERCOM2
		23:16
		31:24
0x1C	INTFLAGC	7:0	TCC7	TCC6	TCC5	TCC4	SERCOM7	SERCOM6	SERCOM5	SERCOM4
		15:8	ETH	PDEC	CCL		SPI_IXS	PTC	AC	ADC
		23:16							USB	TRNG
		31:24
0x20	INTFLAGD	7:0								SQI
		15:8
		23:16
		31:24
0x24 ... 0x33	Reserved
0x34	STATUSA	7:0	OSC32KCTRL	OSCCTRL	RSTC	SUPC	PM	FCW	FCR	DSU
		15:8	TRAM	PAC	EIC	RTC	WDT	FREQM	MCLK	GCLK
		23:16
		31:24
0x38	STATUSB	7:0	SERCOM1	SERCOM0	EVSYS	IDAU	PRM	DMA1	DMA0	PORT
		15:8			TCC3	TCC2	TCC1	TCC0	SERCOM3	SERCOM2
		23:16
		31:24
0x3C	STATUSC	7:0	TCC7	TCC6	TCC5	TCC4	SERCOM7	SERCOM6	SERCOM5	SERCOM4
		15:8	ETH	PDEC	CCL		SPI_IXS	PTC	AC	ADC
		23:16							USB	TRNG
		31:24
0x40	STATUSD	7:0								SQI
		15:8
		23:16
		31:24

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