43.6.12 Register Synchronization

The SYNCBUSY register supports the CTRLA and CTRLB registers. When CTRLA.ENABLE has been set no additional writes to this bit are allowed as long as the SYNCYBUSY.ENABLE bit remains high. Additional writes to the CTRLB register are not allowed as long as the SYNCBUSY.CTRLB bit remains high.

Register synchronization is required for other registers in the GLCK clock domain. These registers can be modified while CTRLA.ENABLE=0, i.e. as long as the ADC is not enabled. Once the ADC is enabled (CTRLA.ENABLE=1) these registers are synchronized to the APB_CLK (Main Clock) domain and are write protected.