43.6.10 Idle and Standby Sleep Mode Operation
The host device supports several modes of operation, starting at Active and ending with Off:
| Mode of Operation: | Behavior: | Wake-Up Signal: |
|---|---|---|
| Active | CPU running. All memory is active. ADC can run. |
None |
| (CPU) Idle | CPU halted. All memory is active. ADC (1) |
All Interrupts |
| Standby | All logic content retained. ADC (1) NVM in sleep mode. Configurable RAM retention support. |
All Interrupts |
| Hibernate | Only backup domain remains active.
ADC cannot run. Configurable RAM retention. Only 32 kHz clock can run. |
Backup Interrupts |
| Backup | Only backup domain remains active.
ADC cannot run. Only 32 kHz clock can run. |
Backup Interrupts |
| Off | Everything is off. | External Reset |
Note:
- The CTRLA.ONDEMAND and CTRLA.RUNSTDBY bits control the behavior of the ADC during Idle and Standby sleep modes, in cases where the ADC is enabled (CTRLA.ENABLE = 1). See the following table:
| CTRLA.ENABLE | CTRLA.RUNSTDBY | CTRLA.ONDEMAND | Description |
|---|---|---|---|
| 0 | x | x | Disabled. |
| 1 | 0 | 0 | ADC inactive in Idle and Standby mode |
| 1 | 0 | 1 | Run in Idle and Standby modes only on EVSYS trigger request. |
| 1 | 1 | 0 | Run in Idle and Standby modes. |
| 1 | 1 | 1 | Run in Idle and Standby modes. |
|
Note: When
CTRLA.ONDEMAND=1, the analog block is always powered-off. When a
start request is detected, the system returns from sleep and starts
a new conversion. When RUNSTDBY is enabled the GCLK to the ADC
continues to run when ONDEMAND=0. With ONDEMAND and RUNSTDBY set the
GCLK will be requested. Therefore, there will be an additional delay
until the analog front end is ready (CTLINTFLAG.CRRDYn=1).
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