34.7.5.8 Status
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUS |
| Offset: | 0x1A |
| Reset: | 0x0000 |
| Property: | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LENERR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TUR | BUFOVF | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 11 – LENERR Transaction Length Error
This bit is set in client mode when the length counter is enabled (LENGTH.LENEN=1) and the transfer length while SS is low is not a multiple of LENGTH.LEN.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
| Value | Description |
|---|---|
| 0 | No Length Error has occurred. |
| 1 | A Length Error has occurred. |
Bit 3 – TUR Frame Transmit Underrun
This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when an underflow condition is detected in frame mode. Writing '0' to this bit has no effect. Writing '1' to this bit sends a request to clear it. It will be actually cleared after the DATA buffer is flushed.
| Value | Description |
|---|---|
| 0 | No Underrun has occurred. |
| 1 | A Underrun has occurred. |
Bit 2 – BUFOVF Buffer Overflow
Reading this bit before reading DATA will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the
bit or by disabling the receiver.
This bit is set when a Buffer Overflow condition is detected. See also CTRLA.IBON for overflow handling.
When set, the corresponding RxDATA will be zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
| Value | Description |
|---|---|
| 0 | No Buffer Overflow has occurred. |
| 1 | A Buffer Overflow has occurred. |