47.6.2.7 Double Buffering

The Pattern (PATT), Period (PER) and Compare Channels (CCy) registers are all double buffered. Each buffer register has a buffer valid (PATTBUFV(STATUS <5>), PERBUFV(STATUS<7>) and CCBUFVy) bit in the STATUS register, which indicates that the Buffer register contains a valid value that can be copied into the corresponding register. As long as a Buffer Valid Status flag (PATTBUFV,PERBUFV or CCBUFVy) is set and the corresponding SYNCBUSY bit is set (SYNCBUSY.PATT(SYNCBUSY<5>),SYNCBUSY.PER(SYNCBUSY<7>) or SYNCBUSY.CCy), a write to the respective PATT/PATTBUF, PER/PERBUF or CCy/CCBUFy registers will generate a PAC error.

When the Buffer Valid Flag bit in the STATUS register is '1' and the Lock Update bit in the CTRLBCLR register is cleared, (writing CTRLBCLR.LUPD(CTRLBCLR<1>) to '1'), update of register by its buffer register is allowed: Data from the buffer register will be copied into the corresponding register under hardware UPDATE conditions, then the Buffer Valid flag bit in the STATUS register is automatically cleared by the hardware.

When the buffer valid flag bit in the STATUS register is '1' (i.e. the buffer register contains a valid value), and the Lock Update bit in the CTRLB register is set to '1', (writing CTRLBSET.LUPD(CTRLBSET<1>) to '1'), update of a register by its buffer register is disabled: Data from buffer register is not copied into the corresponding register on any UPDATE conditions and the buffer valid flag bit in the STATUS register stay unchanged.

A compare register is double buffered as in the following figure.

The registers (PATT/PER/CCy) and corresponding Buffer registers (PATTBUF/PERBUF/CCBUFy) are available in the I/O register map, and the double buffering feature is not mandatory. Double buffering feature can be bypassed by directly writing on (PATT/PER/CCy) registers.

Changing the Period

The counter period can be changed by writing a new TOP value to the register that decides period (PER or CCy, depending on the Waveform Generation Operation), however period update on registers (PER or CCy) is effective after the synchronization delay, irrespective of whether double buffer is enabled or disabled.

A counter wraparound can occur in any Waveform Generation Operation when up-counting without buffering, see the previous figure. COUNT and TOP are continuously compared, so when a new value that is lower than the current COUNT is written to TOP, COUNT will wrap before a compare match. Similarly, unbuffered down-counting operation is shown in the previous figure. Unbuffered operation in dual slope mode is shown in the following figure.

When double buffering is used, the buffer can be written at any time and the counter will still maintain correct operation. The period register is always updated on the update condition, as shown in Changing the Period Using Buffer. This prevents wraparound and the generation of odd waveforms.