34.8.6.1 Control A
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LOWTOUT | SCLSM | SPEED[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SEXTTOEN | SDAHOLD[1:0] | SMBUSEN | PINOUT | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SLEWRATE[1:0] | FILTSEL[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | MODE[2:0] | ENABLE | SWRST | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 30 – LOWTOUT SCL Low Time-Out Enable
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the client will release its clock hold, if enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set.
| Value | Description |
|---|---|
| 0 | Time-out disabled. |
| 1 | Time-out enabled. |
Bit 27 – SCLSM SCL Clock Stretch Mode
This bit controls when SCL will be stretched for software interaction.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | SCL stretch according to I2C Behavioral Diagram (SCLSM = 0) |
| 1 | SCL stretch only after ACK bit according to I2C Client Behavioral Diagram SCLSM = 1 |
Bits 25:24 – SPEED[1:0] Transfer Speed
These bits define bus speed.
These bits are not synchronized.
| Value | Description |
|---|---|
| 0x0 | Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz |
| 0x1 | Fast-mode Plus (Fm+) up to 1 MHz |
| 0x2 | High-speed mode (Hs-mode) up to 3.4 MHz |
| 0x3 | Reserved |
Bit 23 – SEXTTOEN Client SCL Low Extend Time-Out
This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the client will release its clock hold if enabled and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a STOP is received.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | Time-out disabled |
| 1 | Time-out enabled |
Bits 21:20 – SDAHOLD[1:0] SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | DIS | Disabled |
| 0x1 | 75 | 50-100ns hold time |
| 0x2 | 450 | 300-600ns hold time |
| 0x3 | 600 | 400-800ns hold time |
Bit 17 – SMBUSEN SMBus Input Buffer Enable
This bit enables SMBus-compatible I/O logic level.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | SMBus input buffer is disabled. |
| 1 | SMBus input buffer is enabled. |
Bit 16 – PINOUT Pin Usage
This bit sets the pin usage to either two- or four-wire operation:
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | 4-wire operation disabled |
| 1 | 4-wire operation enabled |
Bits 11:10 – SLEWRATE[1:0] Slew Rate Enable
This bit enables the I/O pins slew rate control.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | SM | Standard Mode |
| 0x1 | FM | Fast Mode |
| 0x2 | FMP | Fast Mode Plus |
| 0x3 | HS | High-speed Mode |
Bits 9:8 – FILTSEL[1:0] Input Filter Selection
These bits define filter length applied to the input signals.
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | DIS | Disabled |
| 0x1 | 50F | Minimum 50ns filter (SCL fast mode) |
| 0x2 | 50E | Minimum 50ns filter (SDA even mode) |
| 0x3 | 10 | Minimum 10ns filter |
Bit 7 – RUNSTDBY Run in Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | Disabled – All reception is dropped. |
| 1 | Wake on address match, if enabled. |
Bits 4:2 – MODE[2:0] Operating Mode
These bits must be written to 0x04 to select the I2C client serial communication interface of the SERCOM.
These bits are not synchronized.
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not enable-protected.
| Value | Description |
|---|---|
| 0 | The peripheral is disabled or being disabled. |
| 1 | The peripheral is enabled. |
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in a bus error. Reading any register will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
- When the CTRLA.SWRST is written, the user should poll the SYNCB.SWRST bit to know when the reset operation is complete.
- During a SWRST, access to registers/bits without SWRST are disallowed until the SYNCBUSY.SWRST is cleared by the hardware.
| Value | Description |
|---|---|
| 0 | There is no reset operation ongoing. |
| 1 | The reset operation is ongoing. |