45.6.3.1 HALL Operation Mode

In HALL operation mode, control logic signal 0, 1 and 2 inputs represent the phase A, B and C of a Hall sensor, respectively.

A programmable delayed event can be generated to update a TCC pattern generator.

Figure 45-9. HALL Block Diagram

When positive rotation is detected, the DIR status bit is set (STATUS.DIR = 1). When a negative rotation sequence is detected, the DIR status bit is set (STATUS.DIR = 0).

Figure 45-10. Hall States Overview