34.7.4.4 DMA and Interrupts

Table 34-25. Module Request for SERCOM SPI
Condition Request

DMA

Interrupt
Standard (DRE): Data Register Empty

FIFO (DRE): at least TXTRHOLD locations in TX FIFO are empty

Yes

(request cleared when data is written)

Yes
Standard (RXC): Receive Complete

FIFO (RXC): at least RXTRHOLD data available in RX FIFO, or a last word available and length frame reception completed.

Yes

(request cleared when data is read)

Yes
Standard (TXC): Transmit Complete

FIFO (TXC): Transmit Complete and TX FIFO is empty

N/A Yes
Client Select low (SSL) N/A Yes
Error (ERROR) N/A Yes