18.3.1 Overview
All peripherals are composed of one digital bus interface connected to the APB, AHB, or AXI bus and running from a corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock (GCLK).
Communication between these clock domains must be synchronized. This mechanism is implemented in hardware, so the synchronization process takes place even if the peripheral generic clock is running from the same clock source and on the same frequency as the bus interface.
All registers in the bus interface are accessible without synchronization.
All registers in the peripheral core are synchronized when written. Some registers in the peripheral core are synchronized when read.
Each individual register description will have the properties Read-Synchronized and/or Write-Synchronized if a register is synchronized.
- For registers requiring both read-synchronization and write-synchronization, the corresponding bit in the SYNCBUSY register is shared.
- Due to asynchronicity between the main clock domain and the peripheral clock domains, all Read-Synchronized registers must ensure synchronization is completed before accessing them after waking up from Standby Sleep mode. The respective bit in the Synchronization Busy register (SYNCBUSY) will be cleared when the write-synchronization is complete.
