16.6.1 Write Control

Table 16-1. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	WRCTRL
Offset:	0x00
Reset:	0x00000000
Property:	–


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	KEY[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PERID[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PERID[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 23:16 – KEY[7:0] Peripheral Access Control Key

These bits define the peripheral access control key:

Value	Name	Description
0x0	OFF	No action
0x1	CLEAR	Clear the peripheral write control
0x2	SET	Set the peripheral write control
0x3	LOCK	Set and lock the peripheral write control until the next hardware reset

Bits 15:0 – PERID[15:0] Peripheral Identifier

The PERID represents the peripheral whose control is changed using the WRCTRL.KEY.

Table 16-2. PERID Values
Peripheral	PERID	SFR Suffix	Bit	SFR's
Peripheral	PERID	SFR Suffix	Bit	STATUS	INTFLAG
DSU	0	A	0	STATUSA[0]	INTFLAGA[0]
FCR	1	A	1	STATUSA[1]	INTFLAGA[1]
FCW	2	A	2	STATUSA[2]	INTFLAGA[2]
PM	3	A	3	STATUSA[3]	INTFLAGA[3]
SUPC	4	A	4	STATUSA[4]	INTFLAGA[4]
RSTC	5	A	5	STATUSA[5]	INTFLAGA[5]
OSCCTRL	6	A	6	STATUSA[6]	INTFLAGA[6]
OSC32KCTRL	7	A	7	STATUSA[7]	INTFLAGA[7]
GCLK	8	A	8	STATUSA[8]	INTFLAGA[8]
MCLK	9	A	9	STATUSA[9]	INTFLAGA[9]
FREQM	10	A	10	STATUSA[10]	INTFLAGA[10]
WDT	11	A	11	STATUSA[11]	INTFLAGA[11]
RTC	12	A	12	STATUSA[12]	INTFLAGA[12]
EIC	13	A	13	STATUSA[13]	INTFLAGA[13]
PAC	14	A	14	STATUSA[14]	INTFLAGA[14]
TRAM	15	A	15	STATUSA[15]	INTFLAGA[15]
MBISTINTF	18
TDM	19
FlexRAM	20
PORT	32	B	0	STATUSB[0]	INTFLAGB[0]
DMA0	33	B	1	STATUSB[1]	INTFLAGB[1]
DMA1	34	B	2	STATUSB[2]	INTFLAGB[2]
HMATRIX	35
CMCC	36
PRM	37	B	3	STATUSB[3]	INTFLAGB[3]
IDAU	38	B	4	STATUSB[4]	INTFLAGB[4]
EVSYS	39	B	5	STATUSB[5]	INTFLAGB[5]
SERCOM0	40	B	6	STATUSB[6]	INTFLAGB[6]
SERCOM1	41	B	7	STATUSB[7]	INTFLAGB[7]
SERCOM2	42	B	8	STATUSB[8]	INTFLAGB[8]
SERCOM3	43	B	9	STATUSB[9]	INTFLAGB[9]
TCC0	44	B	10	STATUSB[10]	INTFLAGB[10]
TCC1	45	B	11	STATUSB[11]	INTFLAGB[11]
TCC2	46	B	12	STATUSB[12]	INTFLAGB[12]
TCC3	47	B	13	STATUSB[13]	INTFLAGB[13]
SERCOM4	64	C	0	STATUSC[0]	INTFLAGC[0]
SERCOM5	65	C	1	STATUSC[1]	INTFLAGC[1]
SERCOM6	66	C	2	STATUSC[2]	INTFLAGC[2]
SERCOM7	67	C	3	STATUSC[3]	INTFLAGC[3]
TCC4	68	C	4	STATUSC[4]	INTFLAGC[4]
TCC5	69	C	5	STATUSC[5]	INTFLAGC[5]
TCC6	70	C	6	STATUSC[6]	INTFLAGC[6]
TCC7	71	C	7	STATUSC[7]	INTFLAGC[7]
ADC	72	C	8	STATUSC[8]	INTFLAGC[8]
AC	73	C	9	STATUSC[9]	INTFLAGC[9]
PTC	74	C	10	STATUSC[10]	INTFLAGC[10]
SPI_IXS	75	C	11	STATUSC[11]	INTFLAGC[11]
PCC	76
CCL	77	C	13	STATUSC[13]	INTFLAGC[13]
PDEC	78	C	14	STATUSC[14]	INTFLAGC[14]
CAN0	79
CAN1	80
ETH	81	C	15	STATUSC[15]	INTFLAGC[15]
TRNG	82	C	16	STATUSC[16]	INTFLAGC[16]
SDMCC0	83
SDMCC1	84
USB	85	C	17	STATUSC[17]	INTFLAGC[17]
EBI	86
SQI	96	D	0	STATUSD[0]	INTFLAGD[0]
USBHS	97
HSM	98