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21.6.4 Peripheral BUS Clock Enable Mask0 Register
Note: AHB = Advanced High-performance
Bus
APB = Advanced Peripheral Bus
Table 21-5. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: CLKMSK0 Offset: 0x3C Reset: 0x007F_FFFF Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 MSK22 MSK21 MSK20 MSK19 MSK18 MSK17 MSK16 Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 MSK15 MSK14 MSK13 MSK12 MSK9 MSK8 Access R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0 MSK3 Access R/W Reset 1
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 – MSKn Clock Enable Mask
Bits 8, 9 – MSKn Clock Enable Mask
Bit 3 – MSK3 Clock Enable Mask
Bit Number Module 3 DSU_AHB 4 FCR_AHB 5 FCW_AHB 6 PAC_AHB 8 DMA0_AHB 9 DMA1_AHB 12 PRM_AHB 13 CAN0_AHB 14 CAN1_AHB 15 ETH_AHB 16 SQI_AHB 17 SDMMC0_AHB 18 SDMMC1_AHB 19 USBFS_AHB 20 USBHS_AHB 21 EBI_AHB 22 HSM_AHB
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Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 – MSKn Clock Enable Mask Bits 8, 9 – MSKn Clock Enable Mask Bit 3 – MSK3 Clock Enable Mask
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