1.6 Simulator Execution

The simulator operation is specified in the following topics.

Execution Speed

When MPLAB X Simulator is simulating running in real time, instructions are executing as quickly as the PC's CPU will allow. This is usually slower than the actual device would run at its rated clock speed.

The speed at which the simulator runs depends on the speed of your computer and how many other tasks you have running in the background. The software simulator must update all of the simulated registers and RAM, as well as monitor I/O, set and clear flags, check for break and trace points in software and simulate the instruction with instructions being executed on your computer's CPU.

The execution speed of a discrete-event software simulator is orders of magnitude less than a hardware oriented solution. Slower execution speed may be viewed as a handicap or as a tool. The simulator attempts to provide the fastest possible simulation cycle, and depending upon the mode of operation, can operate on the order of milliseconds per instruction.

Note: Often loops will be used in your code to generate timing delays. When using the simulator, you might wish to decrease these time delays or conditionally remove those sections of your code with “IFDEF” statements to increase simulation speed.

Turning off simulator trace will increase simulation speed by up to 50%. Therefore, use the tracing function only as needed. See 2.2 Using Simulator Trace.

In general, when this discussion says “real time” and you are in the simulator mode, the software simulation is executing simulated code as fast as your PC can simulate the instructions.

Execution on Instruction Cycle Boundaries

The simulator executes on instruction cycle boundaries, and resolutions shorter than one instruction cycle (Tcy) can not be simulated. The simulator is a discrete-event simulator where all stimuli are evaluated, and all responses are generated, at instruction boundaries, which occur at Tcy = 4*Tosc or Tcy = 2*Tosc depending on the device, where Tosc is the input clock period. Therefore, some physical events can not be accurately simulated. These fall into the following categories:

  • Purely asynchronous events
  • Events that have periods shorter than one instruction cycle

The net result of instruction boundary simulation is that all events get synchronized at instruction boundaries, and events smaller than one instruction cycle are not recognized.

The following functions are not supported by the simulation on instruction cycle boundaries:

  • Clock pulse inputs smaller than one cycle even though timer prescalers are capable of accepting clock pulse inputs smaller than one cycle.
  • PWM output pulse resolution less than one cycle.
  • In unsynchronized counter mode, clock inputs smaller than one cycle cannot be used.
  • Showing the oscillator waveform on RC0/RC1 pins.
  • Serial I/O to the pin level.

I/O Timing

External timing in the simulator is processed only once during each instruction cycle. Transient signals, such as a spikes on MCLR smaller than an instruction cycle, will not be simulated.

Note: Stimulus is injected into the simulator prior to the next instruction cycle.