20.6.6.3 Dynamic SleepWalking Based on Peripheral DMA Trigger
To enable this advanced feature, the Dynamic Power Gating for Power Domain 0 and 1 bits in the Standby Configuration register (STDBYCFG.DPGPD0 and STDBYCFG.DPGPD1) have to be written to '1'.
When in retention state, the power domain PD1 (containing the DMAC) can be automatically set to active state if the PM detects a valid DMA trigger that is coming from a peripheral located in PD0. A peripheral DMA trigger is valid if the corresponding DMA channel is enabled and its Run in Standby bit (RUNSTDBY) is written to '1'.
This is illustrated in the following example:
The Analog to Digital Converter (ADC) peripheral is used in one shot measurement mode to periodically convert a voltage level on input pins, and move the conversion result to RAM by DMA. After N conversions, an interrupt is generated by the DMA to wake up the device. In the GCLK module, the ADC generic clock (GCLK_ADC) source is routed to OSCULP32K. RTC and EVSYS modules are configured to generate periodic events to the ADC.
To make the ADC continue to run in standby sleep mode, its Run in Standby (RUNSTDBY) bit is written to '1'. The DMAC is configured to operate in standby sleep mode as well by using its respective RUNSTDBY bit. A DMAC channel is configured to enable peripheral-to-memory transfer from the ADC to the LPSRAM and to generate an interrupt when the block transfer is completed (after N beat transfers). The Run in Standby bit of this DMAC channel is written to '1' to allow it running in standby sleep mode.
The DMAC is configured to operate in standby sleep mode by using its respective RUNSTDBY bit. A DMAC channel is configured to set the DMA destination. The Run in Standby bit of this DMAC channel is written to '1' to allow it running in standby sleep mode.
Entering Standby mode: The Power Manager peripheral sets PD0 (where the ADC peripheral is located), PD1 (the DMAC is located here) and PD2 (CPU) to retention state. The ADC channels are OFF. The GCLK_ADC clock is stopped. The VDDCORE is supplied by the low power regulator.
Dynamic SleepWalking: based on RTC conditions, a RTC event (RTC_PERX) is routed by the Event System to the ADC controller to trigger a single-shot measurement.
This event is detected by the Power Manager which sets the PD0 power domain to active state and starts the main voltage regulator.
After enabling the ADC and starting the GCLK_ADC clock, the single-shot measurement during sleep mode can be performed as a sleepwalking task, refer to the ADC documentation for details. At the end of the comparison, a DMA transfer request (ADC_RESRDY) is triggered by the ADC.
This DMA transfer request is detected by the PM, which sets PD1 (containing the DMAC) to active state. The DMAC requests the CLK_DMAC_AHB clock and transfers the sample to the memory. When the DMA beat transfer is completed, the GCLK_ADC clock and the CLK_DMAC_AHB clock are stopped again, as well as the ADC peripheral.
The low power regulator starts again and the PD0 power domain is set back to retention state by the PM. Note that during this dynamic SleepWalking period, the CPU is still sleeping.
Exiting Standby mode: during SleepWalking with Dynamic Power Gating sequence, if conditions are met, the ADC peripheral generates an interrupt to wake up the device. Successively, the PD1 and PD2 power domain are set to active state by the PM.
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