20.7 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | CTRLA | 7:0 | IORET | |||||||
| 0x01 | SLEEPCFG | 7:0 | SLEEPMODE[2:0] | |||||||
| 0x02 | PLCFG | 7:0 | PLDIS | PLSEL[1:0] | ||||||
0x03 | Reserved | |||||||||
| 0x04 | INTENCLR | 7:0 | PLRDY | |||||||
| 0x05 | INTENSET | 7:0 | PLRDY | |||||||
| 0x06 | INTFLAG | 7:0 | PLRDY | |||||||
0x07 | Reserved | |||||||||
| 0x08 | STDBYCFG | 7:0 | VREGSMOD[1:0] | DPGPD1 | DPGPD0 | PDCFG[1:0] | ||||
| 15:8 | BBIASLP[1:0] | BBIASHS[1:0] | LINKPD[1:0] | |||||||
0x0A ... 0x0B | Reserved | |||||||||
| 0x0C | PWSAKDLY | 7:0 | IGNACK | DLYVAL[6:0] | ||||||