20.6.6.1 Dynamic SleepWalking on Bus Transaction

When in retention state, a power domain can be automatically set to active state by the PM if AHB bus transaction in direction to this power domain is detected. In this device, it concerns the AHB bus transaction from the DMAC to the modules located in power domain PD2.

Dynamic SleepWalking based on bus transaction is illustrated in the example below. By using the Run in Standby bit, the DMAC is configured to operate in standby sleep mode. A DMAC channel is configured to make peripheral-to-memory transfer from a module located in PD1 to the SRAM. Transfer request is triggered by the peripheral at periodic time. Refer to DMAC – Direct Memory Access Controller for details. PD2 is set to active state only when AHB transaction is required before being set to retention state again to save power. Note that during this dynamic Sleepwalking period, the CPU is still sleeping. The device can be woken up by an interrupt, for example at the end of a complete DMA block transfer.