39.15.4 Device Status Bank

Original offset 0x0A & 0x1A

Name: STATUS_BK
Offset: 0x0A
Reset: 0xXXXXXXX
Property: NA

Bit 76543210 
       ERRORFLOWCRCERR 
Access R/WR/W 
Reset xx 

Bit 1 – ERRORFLOW Error Flow Status

This bit defines the Error Flow Status.

This bit is set when a Error Flow has been detected during transfer from/towards this bank.

For OUT transfer, a NAK handshake has been sent.

For Isochronous OUT transfer, an overrun condition has occurred.

For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow errors.

ValueDescription
0 No Error Flow detected.
1 A Error Flow has been detected.

Bit 0 – CRCERR CRC Error

This bit defines the CRC Error Status.

This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank.

0.2.5 Host Registers - Common

ValueDescription
0 No CRC Error.
1 CRC Error detected.