39.12.7 Device Interrupt EndPoint Set n

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Endpoint Interrupt Enable Clear (EPINTENCLR) register. This register is cleared by USB reset .
Name: EPINTENSETn
Offset: 0x109
Reset: 0x0000
Property: PAC Write-Protection

Bit 76543210 
  STALL1STALL0RXSTPTRFAIL1TRFAIL0TRCPT1TRCPT0 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0200202 

Bits 5, 6 – STALL Transmit Stall x Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transmit bank x Stall interrupt.

ValueDescription
0 The Transmit Stall x interrupt is disabled.
1 The Transmit Stall x interrupt is enabled.

Bit 4 – RXSTP Received Setup Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Received Setup interrupt.

ValueDescription
0 The Received Setup interrupt is disabled.
1 The Received Setup interrupt is enabled.

Bits 2, 3 – TRFAIL Transfer Fail bank x Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transfer Fail interrupt.

ValueDescription
0 The Transfer Fail interrupt is disabled.
1 The Transfer Fail interrupt is enabled.

Bits 0, 1 – TRCPT Transfer Complete bank x interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transfer Complete x interrupt.

0.2.4 Device Registers - Endpoint RAM

ValueDescription
0 The Transfer Complete bank x interrupt is disabled.
1 The Transfer Complete bank x interrupt is enabled.