39.12.7 Device Interrupt EndPoint Set n
| Name: | EPINTENSETn |
| Offset: | 0x109 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 2 | 0 | 0 | 2 | 0 | 2 |
Bits 5, 6 – STALL Transmit Stall x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank x Stall interrupt.
| Value | Description |
|---|---|
| 0 | The Transmit Stall x interrupt is disabled. |
| 1 | The Transmit Stall x interrupt is enabled. |
Bit 4 – RXSTP Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Received Setup interrupt.
| Value | Description |
|---|---|
| 0 | The Received Setup interrupt is disabled. |
| 1 | The Received Setup interrupt is enabled. |
Bits 2, 3 – TRFAIL Transfer Fail bank x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
| Value | Description |
|---|---|
| 0 | The Transfer Fail interrupt is disabled. |
| 1 | The Transfer Fail interrupt is enabled. |
Bits 0, 1 – TRCPT Transfer Complete bank x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete x interrupt.
0.2.4 Device Registers - Endpoint RAM
| Value | Description |
|---|---|
| 0 | The Transfer Complete bank x interrupt is disabled. |
| 1 | The Transfer Complete bank x interrupt is enabled. |