20.6.4.4 Regulator Automatic Low Power Mode

In standby mode, the PM selects either the main or the low power voltage regulator to supply the VDDCORE. If all power domains are switchable power domain is in retention state, the low power voltage regulator is used.

If a sleepwalking task is working on either asynchronous clocks (generic clocks) or synchronous clock (APB/AHB clocks), the main voltage regulator is used. This behavior can be changed by writing the Voltage Regulator Standby Mode bits in the Standby Configuration register (STDBYCFG.VREGSMOD). Refer to the following table for details.

Table 20-6. Regulator State in Sleep Mode
Sleep

Modes

STDBYCFG.

VREGSMOD

SleepWalking(1)Regulator state for VDDCORE
Active--main voltage regulator
Idle--main voltage regulator
Standby (at least one PD is active) 0x0: AUTONOlow power regulator
YESmain voltage regulator
0x1: PERFORMANCE-main voltage regulator
0x2: LP(2)-(2)low power regulator
Standby (all PD in retention)--low power regulator
Standby (suspend)-NOoff
Note:
  1. SleepWalking is running on GCLK clock or synchronous clock. This is not related to OSC32K, XOSC32K or OSCULP32K clocks.
  2. Must only be used when SleepWalking is running on GCLK with 32KHz source.