20.8.8 Power Switch Acknowledge Delay
| Name: | PWSAKDLY |
| Offset: | 0xC |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IGNACK | DLYVAL[6:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – IGNACK Ignore Acknowledge signal
| Value | Description |
|---|---|
| 0 | Power Switch acknowledge signal is taken into account when exiting retention mode. According to the DLYVAL field, a supplementary delay is also added (from 0 to 127 digital ring oscillator period). |
| 1 | Power Switch acknowledge signal is ignored when exiting retention mode, and is replaced by a overflow counter signal clocked on internal digital ring oscillator. The overflow counter is programmable by using the DLYVAL field. |
Bits 6:0 – DLYVAL[6:0] Delay value
Value of the counter overflow. See the IGNACK bit description to get more details.