20.8.7 Standby Configuration
| Name: | STDBYCFG |
| Offset: | 0x08 |
| Reset: | 0x0400 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BBIASLP[1:0] | BBIASHS[1:0] | LINKPD[1:0] | |||||||
| Access | R/W | R/W | R | R | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VREGSMOD[1:0] | DPGPD1 | DPGPD0 | PDCFG[1:0] | ||||||
| Access | R | R | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 13:12 – BBIASLP[1:0] Back Bias for HMCRAMCLP
Refer to Table 20-5 for details.
| Value | Description |
|---|---|
| 0 | Retention Back Biasing mode (Memory is back-biased when the power domain is in RET mode) |
| 1 | Standby Back Biasing mode (Memory is back-biased when the chip is in standby mode) |
| 2 | Standby OFF mode (Memory is in ultra-back-biasing mode when the chip is in Standby mode) |
| 3 | Always OFF mode (Memory is in ultra-back-biasing mode without condition) |
Bits 11:10 – BBIASHS[1:0] Back Bias for HMCRAMCHS
Refer to Table 20-5 for details.
| Value | Description |
|---|---|
| 0 | No Back Biasing in Standby mode |
| 1 | Back Biasing in Standby mode (Memory is back-biased when the chip is in standby mode) |
| 2 | Standby OFF mode (Memory is in ultra-back-biasing mode when the chip is in Standby mode) |
| 3 | Always OFF mode (Memory is in ultra-back-biasing mode without condition) |
Bits 9:8 – LINKPD[1:0] Linked Power Domain
Refer to Linked Power Domains for details.
| Value | Name | Description |
|---|---|---|
| 0x0 | DEFAULT | Power domains PD0/PD1/PD2 are not linked. |
| 0x1 | PD01 | Power domains PD0 and PD1 are linked. If PD0 is active, then PD1 is active even if there is no activity in PD1 . |
| 0x2 | PD12 |
Power domains PD1 and PD2 are linked. If PD1 is active, then PD2 is active even if there is no activity in PD2. |
| 0x3 | PD012 |
All Power domains are linked. If PD0 is active, then PD1 and PD2 are active even if there is no activity in PD1 or PD2. |
Bits 7:6 – VREGSMOD[1:0] VREG Switching Mode
Refer to Regulator Automatic Low Power Mode for details.
| Value | Name | Description |
|---|---|---|
| 0x0 | AUTO | Automatic Mode |
| 0x1 | PERFORMANCE | Performance oriented |
| 0x2 | LP | Low Power consumption oriented |
Bit 5 – DPGPD1 Dynamic Power Gating for Power Domain 1
| Value | Description |
|---|---|
| 0 | Dynamic SleepWalking for power domain 1 is disabled. |
| 1 | Dynamic SleepWalking for power domain 1 is enabled. |
Bit 4 – DPGPD0 Dynamic Power Gating for Power Domain 0
| Value | Description |
|---|---|
| 0 | Dynamic SleepWalking for power domain 0 is disabled. |
| 1 | Dynamic SleepWalking for power domain 0 is enabled. |
Bits 1:0 – PDCFG[1:0] Power Domain Configuration
| Value | Name | Description |
|---|---|---|
| 0x0 | DEFAULT | In standby mode, all power domain switching are handled by hardware.(based on event, DMA trigger, clock request, or AHB transaction request) |
| 0x1 | PD0 | In standby mode, power domain 0 (PD0) is forced ACTIVE. Other power domain switching is handled by hardware. |
| 0x2 | PD01 | In standby mode, power domains PD0 and PD1 are forced ACTIVE. Power domain 2 switching is handled by hardware. |
| 0x3 | PD012 | In standby mode, all power domains are forced ACTIVE. |