35.7.1.5 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
   MC1MC0  ERROVF 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 4, 5 – MCx Match or Capture Channel x Interrupt Enable

Writing a '0' to these bits has no effect.

Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the Match or Capture Channel x interrupt.

ValueDescription
0 The Match or Capture Channel x interrupt is disabled.
1 The Match or Capture Channel x interrupt is enabled.

Bit 1 – ERR Error Interrupt Disable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.

ValueDescription
0 The Error interrupt is disabled.
1 The Error interrupt is enabled.

Bit 0 – OVF Overflow Interrupt Disable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request.

ValueDescription
0 The Overflow interrupt is disabled.
1 The Overflow interrupt is enabled.