4.1 Revision History

• Document: General editorial updates

• Added Errata for silicon Rev. B0:
  • Device: 2.2.4 Write Operation Lost if Consecutive Writes to Specific Address Spaces
  • NVMCTRL: 2.7.2 NVM_EEPROM_ERASE Command does Not Respect Write Protect
  • PORT: 2.9.1 PD0 Input Buffer is Floating
  • TCD: 2.14.3 Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is 0 or Dual Slope Mode is Used
  • TWI: 2.15.2 Flush Non-Functional
  • USART: 2.16.3 Receiver Non-Functional after Detection of Inconsistent Synchronization Field

• Added Data Sheet Clarifications:
  • SPI: 3.1.1 SPI - Serial Peripheral Interface
  • SPI: 3.1.2 SPI - Serial Peripheral Interface
  • Electrical Characteristics: 3.2.1 I/O Pins
  • Electrical Characteristics: 3.2.2 SPI

• Added Errata:
  • SPI: 2.11.1 Alternative 2 Pin Position is Non-Functional for SPI1 with 48-Pin Devices
  • USART: 2.16.3 Receiver Non-Functional after Detection of Inconsistent Synchronization Field
• Document: General editorial updates
• Removed all data sheet clarifications as they are fixed in the current device data sheet ( www.microchip.com/DS40002247 )

Document: General editorial updates.

• Device: 2.2.3 CRC Check During Reset Initialization Is not Functional
• CLKCTRL: 2.5.3 PLL Status not Working as Expected
• DAC: 2.6.1 DAC Output Buffer Lifetime Drift
• NVMCTRL: 2.7.1 Flash Multi-Page Erase Can Erase Write Protected Section
• TCA: 2.12.1 Restart Will Reset Counter Direction in NORMAL and FRQ Mode
• TCD: 2.14.3 Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is 0 or Dual Slope Mode is Used
• TWI: 2.15.2 Flush Non-Functional

• 2.16.2 Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode

• Features
• FUSE - Configuration and User Fuses - SYSCFG0
• Peripherals and Architecture - REVID
• Voltage Regulator Control (VREGCTRL)
• Single-Shot Mode
• Analog Comparator Interrupt Control
• DAC Output
• Electrical Characteristics - Memory Programming Specifications

• Device: Increased Current Consumption May Occur When VDD Drops
• CLKCTRL: The PLL Will Not Run When Using XOSCHF With an External Crystal
• TCB: CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode
• TCD:
  • Asynchronous Input Events Not Working When TCD Counter Prescaler is Used
  • CMPAEN Controls All WOx For Alternative Pin Functions

• CCL:
  • The CCL Must be Disabled to Change the Configuration of a Single LUT
  • The LINK Input Source Selection for LUT3 is Not Functional on 28- and 32- pin Devices
• ZCD: All ZCD Output Selection Bits are Tied to the ZCD0 Bit

Added Typical Characteristics section with additional plots for OPAMP peripheral.